1. Field of the Invention
The present invention relates to a static memory, and more particularly to a memory cell which uses a semiconductor memory device that has a multi-port function.
2. Description of the Prior Art
With a recent advancement in the semiconductor technology, there have been developed semiconductor memory devices that possess various functions. For instance, there exists a memory device which, having the so-called multi-port memory cell connected to a plurality of word lines and data lines, can carry out the read or write operation for a plurality of memory cells independently of each other and in parallel. The usefulness of the multi-port memory device is being appreciated increasingly as the memory device for the microcomputers that are being employed extensively for a wide range of purposes, for improving the performance of the microcomputers.
In FIG. 1 is shown a circuit diagram for one bit portion of a memory cell of a 2-port memory device. The writing operation in the memory cell is carried out by memorizing a high or low level voltage information that is given to the respective bit lines BL1 and BL1, and an inverted low or high level voltage information that has logic which is the inverse of that of said voltage information, in a bistable circuit 9 which consists of inverters 5 and 7 that have their mutual input-output terminals connected via transfer gates 1 and 3 whose conduction is controlled by the potential of a word line WL1. In addition, writing is carried out also by memorizing a voltage information and an inverted voltage information that are given respectively to bit lines BL2 and BL2, in the bistable circuit 9 via transfer gates 11 and 13 whose conduction is controlled by the potential of a word line WL2.
Further, the reading operation of the memory cell is carried out by delivering a voltage information and an inverted voltage information that are memorized in the bistable circuit 9 to the bit lines BL1 and BL1 via the transfer gates 1 and 3. Or, the reading is carried out by delivering a voltage information and an inverted voltage information that are memorized in the bistable circuit 9 to the bit lines BL2 and BL2 via the transfer gates 11 and 13.
In this way, the writing operation or the reading operation can be carried out in parallel and independently for two arbitrary memory cells that are arranged in matrix-form, by connecting two word lines and four bit lines to one memory cell. In a memory cell with such a configuration, however, there are required two pairs of bit lines which results in an increase in the occupied area of the memory cell to that of the memory device as a whole, becoming an obstruction to the attempt to increase the degree of integration.
The memory cell shown in FIG. 2 is one in which the memory cell is designed to function as a 3-port device (one write only port and two read only ports) with three bit lines, by decreasing the number of bit lines in FIG. 1 by one.
In this memory cell, reading operation is carried out by delivering the voltage information memorized in the bistable circuit 9 to the bit line BL2 via the transfer gate 15 whose conduction is controlled by the potential of the word line WL2, or by delivering the voltage information to the bit line BL3 via the transfer gate 17 whose conduction is controlled by the potential of the word line WL3. In addition, reading operation of the memory cell is designed to be carried out by using just one bit line BL1.
In order for the bistable circuit 9 to accurately memorize voltage information using a single bit line BL1, it is necessary to assign a larger driving capability to the inverter circuit 19 than that of the inverter circuit 21 that form together the bistable circuit 9. For this reason, the determination of the ratios of the inverter circuit 19 and the inverter circuit 21 to the transfer gate 1 is difficult to achieve which leads to a complication in the memory cell design. In addition, since the inverter circuit 19 and the inverter circuit 21 are asymmetric, the occupied area of the memory cell, for which is required the highest degree of integration in the memory device, is increased. Also, there is the necessity of preparing the word lines and the bit line for exclusive in reading and writing. Again it can be seen that it is not easy in such a memory cell configuration to increase the degree of integration.
The memory cell shown in FIG. 3 is designed to give an equal size to the inverter circuits 23 and 25 that constitute the bistable circuit 9, in contrast to the memory cell in FIG. 2, and the writing operation is designed to be carried out by using two bit lines BL1 and BL2. The reading operation is carried out by using the bit line BL2 or bit line BL3. When, in a memory cell with such configuration, the voltage information memorized in the bistable circuit 9 is to be delivered simultaneously via the transfer gates 15 and 17 to the respective bit lines BL2 and BL3, if the bit lines BL2 and BL3 are in a high level state (for instance, 5 V) and the potential at the point A of the bistable circuit 9 is in a low level state (for instance, 0 V), then the currents flow to the point A from both bit lines BL2 and BL3, raising the potential of the point A. Because of this, in the worst situation, the inverter circuit would carry out an inverting operation to bring the potential of the point B to a low level state and the potential of the point A to a high level state, there is a fear of having a case in which the voltage information memorized in the bistable circuit 9 is rewritten.
Further, in delivering the voltage information memorized in the bistable circuit 9 simultaneously to the two bit lines BL2 and BL3, load on the inverter circuit 23 will be doubled compared with the case of delivering it using either one of the bit lines. Consequently, there will be generated a problem that the reading time will become increased.